The trend for semiconductor devices is smaller integrated circuit devices (IC devices, also referred to as chips), packaged in smaller packages (which protect the chip while providing off chip signaling connectivity). 3D packaging, in which related chips are stacked inside a single package, has recently been developed and refined. 3D packaging can result in increased density and smaller form factor, better electrical performance (because of shorter interconnect length which allows for increased device speed and lower power consumption), better heterogeneous integration (i.e. integrate different functional layers such as an image sensor and its processor), and lower cost. Existing 3D IC packaging techniques used to form through-silicon via's (TSV's), including Via-First, Via-Last and Via-middle processes, utilize semiconductor lithographic processes which are inherently complex and costly. As a result, few companies in the world can afford the billions of dollars in CMOS R&D per year to keep pace.
Another related 3D packaging technology is the interposer. A conventional interposer is an insulation substrate (typically plastic or ceramic) with conductive patterns formed on, in and/or through the substrate to provide an electrical interface for semiconductor devices. Interposers are commonly used for chip assembly techniques employing the flip-chip method of using solder balls to create the electrical connections between the chip and the interposer. The interposer can provide electrical connections having a modified, increased, or decreased connection pattern or density relative to the electrical connection pattern or density on the semiconductor device.
More recently, with the advent of through-silicon vias, 3D silicon and glass interposers have been developed to increase the gap between printed circuit boards and integrated circuits, both in terms of geometries and materials, for use in System-in-Package (SiP), Package-on-package (PoP), flip-chip Ball grid Array (fc-BGA) or more recently fan-out Wafer Level Packaging. 3D interposers combine wafer-level techniques and advantages with 3D routing capabilities (e.g. higher resolution and finer pitches/densities).
A conventional 3D interposer is illustrated in FIG. 1. The interposer 1 includes a silicon substrate 2, through silicon via's 3 extending through and forming an electrical contact through the substrate 2, routing layers 4 and SMT compatible contacts 5, flip chip connectors 6 (on which an IC chip 7 is mounted). One difficulty in manufacturing the interposer 1 involves the via's 3, which are difficult to fabricate as the width of the substrate 2 increases (e.g. requires expensive semiconductor sputtering tools). Moreover, the SMT contacts 5 between the interposer 1 and the underlying printed circuit board can fail due to thermal stress caused by the different thermal and mechanical characteristics between the interposer and PC board on which the interposer is mounted. A complementary, cost-effective TSV solution is needed to enhance the performance of 3D interposers.